西瑪西瑪電機(jī) if(!der) reg[3:0] out; case(current1) else current1 < =s7; end if(cnt < = 4000) cnt < = cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 current1 < =s4; begin out < =4'b0011; a=~a; else if(temp==3'd1) s0: else a=~a; out < =4'b1100; else end always @(posedge clk1) module step2 (clk1,a,adj);//分頻module else reg[2:0] current; end begin current1 < =s2; begin current < =s7; begin current < =s0; end step2 l1 (clk,p,d);//clk系統(tǒng)時(shí)鐘 end end s3: end begin end else end begin current1 < =s1; end endmodule begin cnt < =26'b0; end current < =s1; begin if(!der) begin begin if(!der) endmodule

主要思想，用狀態(tài)機(jī)驅(qū)動(dòng)步進(jìn)西瑪電機(jī)�。�！

總體感覺，整個(gè)程序比較繁瑣，看見別人實(shí)現(xiàn)相同的功能代碼也才那么幾十行，我的……呃 差距可想而知了。。。
current<=s5; end always@(current1 )//or clk0 current<=s0; temp=adj[5]+adj[4]+adj[3]+adj[2]+adj[1]+adj[0]; end output [3:0]out; if(!reset) end cnt <=26'b0; s2: endcase current1<=s7; begin s5: begin end current<=s5; current<=s4; cnt <=26'b0; begin end current1<=s4; end out<=4'b0110; begin output a; end end end end end else if(temp==3'd2) if(!der) end module step (clk,reset,out,der,d);//總體模塊d[5:0]調(diào)速控制端口 用6個(gè)撥碼開關(guān)表示 全1速度最慢 全0時(shí)速度最快 其中1（0）的個(gè)數(shù)能表示西瑪電機(jī)速度的快慢 else if(temp==3'd0) current1<=s1; s3: reg[2:0] current1; end if(cnt <= 8000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 current<=s6; begin out<=4'b0010; begin a=~a; end begin parameter s0=3'b000,s1=3'b001,s2=3'b010, input clk1; if(!der) s7: end reg[25:0] cnt; begin else step1 l2 (p,reset ,out,der);//reset停止轉(zhuǎn)動(dòng) out[3:0]西瑪電機(jī)控制輸出端口 der正反方向控制端 begin current1<=s5; begin else begin s4: s2: end end s6:

這兩天，學(xué)校做關(guān)于cpld的課程設(shè)計(jì)，本來應(yīng)該用VHDL寫的，但是由于我對(duì)這個(gè)比較白癡，所以就選用Verilog HDL寫了，由于旁邊有同學(xué)是學(xué)這個(gè)的這樣，有什么問題也好解決一點(diǎn)。下面就先把我Verilog HDL的處女作給大家貼出來，雖然功能比較簡(jiǎn)單，但畢竟也是第一個(gè)程序嘛。。。 module step1 (clk0,reset,out,der,x);//狀態(tài)機(jī)module out<=4'b0001; current<=s0; current1<=s3; begin end cnt <=26'b0; begin begin s1: else if(temp==3'd4) begin current<=s7; endcase begin begin current<=s3; else input clk ,reset,der,d; else if(temp==3'd5) current1<=s0; end begin begin begin end input clk0,reset,der,x; begin reg[2:0] temp; a=~a; current<=s4; begin end current1<=s6; out<=4'b1001; end reg a; current<=s2; a=~a; wire[5:0] adj; current1<=s3; begin if(!der) end wire p; a=~a; else begin current1<=s0; s1: begin else if(!der) out<=4'b0100; end begin else begin begin current<=s1; end begin end begin if(!der) end begin begin end if(temp==3'd6) if(cnt <= 32000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 current<=s3; end end s6: reg[15:0] counter; begin cnt <=26'b0; case(current) endmodule current<=s6; begin if(cnt <= 16000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 end else else if(temp==3'd3) current<=s2; begin end always@(posedge clk0 or negedge reset ) end s6=3'b110,s7=3'b111; cnt <=26'b0; input[5:0] adj; s3=3'b011,s4=3'b100,s5=3'b101, cnt <=26'b0; if(cnt <= 12000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 current1<=s6; begin end s4: else a=~a; end end current1<=s5; wire[5:0] d; if(cnt <= 6000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 out<=4'b1000; begin else begin begin s7: s5: end end end s0: begin output[3:0] out; if(cnt <= 10000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000 current1<=s2; else else 西瑪西瑪電機(jī)